module servo (
    input clk,
    input reset,
    input highcont,
    output reg pwm
);
    parameter  hightime=1.5;
    //周期20ms clk=27MHz
    //分频0.1ms
    reg [11:0] cont;
    parameter cont_max = 2700-1;
    reg msclk;
    always @(posedge clk or negedge reset) begin
        if (reset==0) begin
            cont<=0;
            msclk<=0;
        end else begin
            if (cont==cont_max) begin
                msclk<=1;
                cont<=0;
            end else begin
                cont<=cont+1;
                msclk<=0;
            end
        end
    end

    reg [7:0] mscnt;//0.1ms计数一次
    always @(posedge clk or negedge reset) begin
        if (reset==0) begin
            pwm<=0;
            mscnt<=0;
        end else begin
            if (msclk==1) begin
                if (mscnt==20-1) begin
                    mscnt<=0;
                end else begin
                    mscnt<=mscnt+1;
                end      
            end 
            if ((mscnt<hightime*10)-1) begin
                pwm<=1;
            end else begin
                pwm<=0;
            end
        end
    end
endmodule

`timescale 1us/1us

module servo_tb ();
    reg clk;
    reg reset;
    wire pwm;
    servo myservo(
        .clk(clk),
        .reset(reset),
        .pwm(pwm)
    );
    always #1 clk<=~clk;
    initial begin
                clk<=0;reset<=0;
        #10    reset<=1;
        #50000 $stop;
    end

endmodule
